Open Source Flight Controller/Altimeter

[konkers]

I've finished with the first draft of the EVT2 schematic and uploaded it to https://oss.tekno.us/flightcon/hardware.php . Any comments are appreciated.

-Erik

 

[dixontj93060]

Erik,

Looks like it is progressing well. Can't wait for availability!

-Tim

 

[UhClem]

Originally posted by konkers
I've finished with the first draft of the EVT2 schematic and uploaded it to https://oss.tekno.us/flightcon/hardware.php . Any comments are appreciated.

-Erik

Please explain the 7407 buffer. It can't be to interface between 3.3V and 5V for various reasons:

1) The TTL input level for a logic high is higher than the level required by the AD7708 Plus it sucks a lot of current for a logic zero. Or perhaps you intend to use one of the CMOS variants.
2) When interfacing between a lower voltage and higher, the driver is always powered off of the lower voltage. Then the OC outputs will pull down to zero and the resistors pull up to the desired voltage.
3) The AD7708 has separate digital and analog power supplies so the digital side could run on 3.3V.

Also, how do you get greater than 500 SPS (mentioned earlier) out of a AD7708 when converting multiple channels.

 

[falingtrea]

Dave, the 7407 is an open collector device that only pulls the outputs down to 0V. You need pull ups for a high so you can us 5V or 3.3V or even 12V or 24V on the pull up resistor. So the trick is to pick the right pull up resistor value.

As for the sample rate, I am not too familiar with sigma delta ADCs but the date sheet talks about a max update rate of 100 Hz. I am not sure if that means 100 sample per second, but considering it has a 32kHz sample clock, that is plasible. You can get up to 1.3kHz if you turn chop off, but that is not recommended if you are changing channels between samples.

 

[konkers]

Originally posted by UhClem
Please explain the 7407 buffer. It can't be to interface between 3.3V and 5V for various reasons:

1) The TTL input level for a logic high is higher than the level required by the AD7708 Plus it sucks a lot of current for a logic zero. Or perhaps you intend to use one of the CMOS variants.
2) When interfacing between a lower voltage and higher, the driver is always powered off of the lower voltage. Then the OC outputs will pull down to zero and the resistors pull up to the desired voltage.

yeah... I'm using the SN74LV07. the symbol just says 7407

3) The AD7708 has separate digital and analog power supplies so the digital side could run on 3.3V.

You know, I mis-read the datasheet and go the impression that AVdd had to be less than DVdd. Looks like you're right. I'm happy to take out the level conversion. Thanks!

Also, how do you get greater than 500 SPS (mentioned earlier) out of a AD7708 when converting multiple channels.

I'm planning on sampling the accelerometer every other cycle. This is the only data source I believe benefits from that high sample rate.

-Erik

 

[konkers]

Originally posted by falingtrea
Dave, the 7407 is an open collector device that only pulls the outputs down to 0V. You need pull ups for a high so you can us 5V or 3.3V or even 12V or 24V on the pull up resistor. So the trick is to pick the right pull up resistor value.

As for the sample rate, I am not too familiar with sigma delta ADCs but the date sheet talks about a max update rate of 100 Hz. I am not sure if that means 100 sample per second, but considering it has a 32kHz sample clock, that is plasible. You can get up to 1.3kHz if you turn chop off, but that is not recommended if you are changing channels between samples.

I guess I was planning on running with the chop disabled... but now reading the datasheet more closely, it does seem to be not the best idea. Also running at 1.3KHz looks like it reduces my effective data width to 8bits which is useless. Any suggestions on ADCs would be appreciated.

Thanks,
Erik

 

[UhClem]

Originally posted by konkers
yeah... I'm using the SN74LV07. the symbol just says 7407

You know, I mis-read the datasheet and go the impression that AVdd had to be less than DVdd. Looks like you're right. I'm happy to take out the level conversion. Thanks!


I'm planning on sampling the accelerometer every other cycle. This is the only data source I believe benefits from that high sample rate.

-Erik

The data sheet says: "AVDD and DVDD can be operated independently of each other, allowing the device to be operated with 5 V analog supply and 3 V digital supply or vice versa."

You cannot sample the accel every other cycle as you must wait several settling times after changing configuration for the data to work its way through the sigma delta converter. This cuts the sample rate by a quarter.

"A synchronized step change will require a settling time of three times the programmed update rate, a channel change can be treated as a synchronized step change."

This is a "feature" of sigma-delta converters.

 

[konkers]

Originally posted by UhClem

"A synchronized step change will require a settling time of three times the programmed update rate, a channel change can be treated as a synchronized step change."

This is a "feature" of sigma-delta converters.

Hrm, going back to the two TI 1 channel 12 bit ADCs is starting to seem attractive.

-Erik